1. Field of the Invention
The present invention relates to a method for setting erasing pulse determining the number of or time for applications of the erasing pulses in a block erasing operation where a target block which consists mainly of a number of memory cells to be erased in a nonvolatile memory is erased by applying the erasing pulses plural times for erasing its block data together. Also, the present invention relates to a method for screening erasing defects in the nonvolatile memory and, more particularly, to a screening method capable of specifying defective memory cells which are slower in the erasing operation than the normally erased memory cells.
2. Description of the Related Art
A typical example of the nonvolatile memory is a flash erasable, electrically programmable read-only memory (flash EEPROM) including an electrically insulated MOS gate called a floating gate (see “A Single Transistor EEPROM Cell and Implementation in 512 k CMOS EEPROM” by S. Mukherjee et. al, IEDM Technical Digest, p. 616, 1985).
FIG. 1 illustrates a memory cell structure of such a conventional flash EPROM. The structure has a layer arrangement where the floating gate 1 is disposed to control directly a channel 2 and store data (electrons) and a control gate 4 is stacked over the floating gate 1 via an insulating layer 3. As apparent from an equivalent circuit shown in FIG. 2, the floating gate 1 is isolated from the external terminals by the insulating layer and its potential is controllably determined by capacitance coupling of the four external terminals. As the data writing operation is based on the mechanism of hot carrier phenomenon which is equal to the principle of writing operation on an ultraviolet ray erasable EPROM, it allows the electrons to be loaded with a higher level of energy than the barrier height of a tunnel gate oxide layer 5 serving as the insulating layer and injected in the floating gate 1. The erasing operation based on the mechanism of Fowler-Nordheim tunnel phenomenon involves releasing the electrons across the tunnel oxide layer 5 of an overlap region between the floating gate 1 and the source diffusion 6. This can control the number of electrons in the floating gate 1. The reading operation which is equal to that of a common NOR type MOS memory involves sensing a difference in the driving current for the accumulated data (the number of electrons) in each memory cell selectively activated through the bit line (drain 7) and the word line (control gate 4).
A conventional erasing operation for a nonvolatile memory involves applying an erasing voltage to a number of memory cells (bits) at once in a target block to be erased simultaneously. FIG. 3 is a flowchart showing a procedure of the erasing operation of a control circuit over the target block in a memory cell array.
The procedure starts with setting an erasing voltage generation circuit with a voltage condition for the erasing operation (step 301). A target block to be erased is selected (step 302). As the erasing pulses have been applied (step 303), unerased bits are counted at the erase verification level (reference threshold voltage for verification) (step 304). When the number of unerased bits is not zero (step 305), the procedure repeats a loop of the pulse applying operation in step 303 and the unerased bit counting operation in step 304 until the number of unerased bits turns to zero or the number of applications of the erasing pulses reaches its maximum.
The erasing operation for a conventional flash EPROM is disclosed with an erasing algorithm in JP-A 02-10596.
The erasing operation on the conventional nonvolatile memory involves applying an erasing voltage to a number of memory cells (bits) at once in a target block to be erased simultaneously. Since all the bits in the target block to be erased are subjected at once to the erasing operation, the distribution of threshold voltages after the erasing operation which is ideally a normal distribution as denoted by (a) in FIG. 4 may be interrupted by various factors in the manufacturing process thus exhibiting irregular groups of bits (b) and (c) off the normal distribution. The bit group (b) is called over erased bits. When the threshold voltage in the memory cells is too low, it may increase leaks during the readout operation from unselected memory cells connected to the common bit lines, whereby the readout current at the memory cells will hardly be determined (erroneous readout). The bit group (c) is called slowly erased bits. The erasing operation in the prior art includes monitoring the number of unerased bits at the erase verification level (reference threshold voltage for verification) or the number of bits higher than the threshold voltage of the erase verification level. When the number of unerased bits turns to zero, the erasing operation is ended. If a group of slowly erased bits (c) exist, an extra number of erasing pulses is applied for decreasing the threshold voltage to lower than the erase verification level. As a result, the threshold voltage will be declined to a much lower level with the ideal normal distribution (a) and the over erased bit group (b) than that where the bit group (c) is absent. This will increase the number of memory cells at lower levels of the threshold voltage, permitting the unselected memory cells to be read out with difficulty due to the occurrence of off-leak currents.
For screening the defective bits (c), the method of the prior art includes presetting the maximum of erasing pulse application time, conducting the erasing operation through a procedure shown in FIG. 3, and discarding as the slowly erased bits unerased bits which are unerased when the pulse application time has exceeded its preset absolute maximum. FIG. 5 illustrates a profile of distribution of the threshold voltages when the maximum number of erasing pulses has been applied.
However, the erasing operation depends largely on and may be disturbed in the characteristics by the effect of variations in the factors at the manufacturing process which include the tunnel oxide layer thickness, the coupling rate of the floating gate, and the threshold voltage at the erasing operation with ultraviolet ray. It will be very difficult for conducting the erasing operation with a margin not to over-kill the normal distribution because the variations declining the accuracy are eliminated only at the area denoted by (d) in FIG. 5. Also, as the width (e) of the distribution of the threshold voltages shown in FIG. 4 is varied during the manufacturing process, it will additionally decline the accuracy.
The method of the prior art includes a sequence of controlling the memory array control circuit provided on a chip form of the memory where the number of unerased bits is counted (examined) whenever the erasing pulses are applied. As the result, the erasing operation will be increased in the time consumption by a length expressed by (the total number of erasing pulses×the time for examining unerased bit number).